I2S [Inter-IC Sound, Integrated Interchip Sound, or IIS]

I started working on audio related task from November 2012. Till now my journey in audio world is amazing. Though I faced many issues during initial days, my love towards audio did not reduce. As I am currently working on I2S protocol thought of writing this article. 

 

I2S is a serial bus interface standard used for connecting digital audio devices together. Digital audio is obtained by quantizing and sampling sound [Analog data].

This standard was introduced in 1986 and was last revised in 1996 by Philips.

I2S is a 3 wire interface. It contains:

         Bit clock line[BCK] 

         Word clock line[WS] 

         Data  line[DATA]

Bit Clock line [BCK]

Clock line is used for synchronization; such devices ignore their inputs except at the transition of a dedicated clock signal. Circuits using the clock line for synchronization will become active at the rising edge, falling edge, high or low level of bit clock.

Data line [DATA]

This is a time division multiplexed data line. Two channels [Left and Right] are multiplexed and sent over a single data line.

Data is transmitted in two’s complement with the MSB Byte first. Sending MSB Byte first has an advantage which I will explain later.

Word clock line [also known as word-selectWS]

The word select line tells us which channel data the bus is currently holding. If WS is 0, bus is currently holding Left channel data. If WS is 1, bus is currently holding Right channel data.WS may change either on a trailing or leading edge of the Bit clock.

The I2S design ensures handling of audio data separately from clock signals. This means clock signal is not embedded inside audio data. By separating data and clock signals results in very less jitter.

Whichever module [Transmitter/Receiver] generates clock and word select becomes master.

If you observer figure 1 you can observer that WS and BCK are pointing outwards transmitter and pointing inwards receiver. In this case Transmitter is Master Transmitter as it is generating clock and sending data.Receiver is Slave Receiver.

If you observer figure 2 you can observer that WS and BCK are pointing inwards transmitter and pointing outwards receiver.In this case Receiver is Master Receiver as it is generating clock and receiving data. Transmitter is Slave Transmitter.

One should know about word width to understand advantage of sending MSB Byte first. Word width is how many digits are used to represent a value in a digital word. In Figure 3 you can see that sine wave is quantised and sampled into 4 values[0,1,2,3] which require 2 bits to represent 4 values[ 00,01,10,11]. So the word length is 2 bit.

Figure 3

Transmitter and Receiver may have different word lengths. The advantage of sending MSB first is that if the receiver is sent more bits than its word length, the bits after the LSB are just ignored.This means there is data loss but I2S ensures the lost data has least impact by sending MSB first.If the receiver is sent fewer bits than its word length, the missing bits are set to zero.

The transmitter always sends the MSB of the next word one clock period after the WS changes. You can see this is Figure 4.

                                                                                         

Figure 4